Datasheet

DS21Q59 Quad E1 Transceiver
59 of 76
Figure 24-7. Transmit Interleave Bus Operation
TSER
LSB
SYSCLK
TSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
MSB LSB
FRAMER 1, CHANNEL 1
4
TSER
TSYNC
TSER
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
1
2
BIT DETAIL
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
NOTE 1: 4.096MHZ BUS CONFIGURATION.
NOTE 2: 8.192MHZ BUS CONFIGURATION.
NOTE 3: 16.384MHZ BUS CONFIGURATION.
NOTE 4: TSYNC IS IN THE INPUT MODE (TCR.0 = 0). TSYNC MAY BE HELD HIGH FOR MULTIPLE CLOCK CYCLES AS LONG AS IT
TRANSITIONS LOW ONE CLOCK CYCLE BEFORE TRANSITIONING HIGH AGAIN FOR THE NEXT SYNC PULSE.
TSER
FR4 CH32
FR5 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
3
FR6 CH32
FR7 CH32
FR4 CH1
FR5 CH1
FR6 CH1
FR7 CH1
FR5 CH2
FR6 CH2