Datasheet

DS21Q59 Quad E1 Transceiver
51 of 76
21.3.2 Undedicated Clock Jitter Attenuator
The undedicated jitter attenuator is useful for preparing a user-supplied clock for use as a transmission clock
(TCLK). AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of PLL or other
synthesizers can contain too much jitter to be appropriate for transmission. Network requirements limit the amount
of jitter that can be transmitted onto the network. This feature is enabled by setting SC1CR.7 = 1 in Transceiver 1.
Figure 21-4. Jitter Tolerance
Figure 21-5. Jitter Attenuation
FREQUENCY (Hz)
UNIT INTERVALS (UI
P-P
)
1k
100
10
1
0.1
10 100 1k 10k 100k
DS21Q59
TOLERANCE
1
MINIMUM TOLERANCE
LEVEL AS PER
ITU G.823
40
1.5
0.2
20
2.4k
18k
FREQUENCY (Hz)
0
-20
-60
1
10 100 1k 10k
JITTER ATTENUATION (dB)
100k
ITU G.7XX
PROHIBITED AREA
ETS 300 011 AND TBR12
PROHIBITED AREA
40
-40
JITTER ATTENUATION CURVE