Datasheet

DS21Q59 Quad E1 Transceiver

23 of 76

8.5 Local Loopback

When CCR4.6 is set to 1, the DS21Q59 is forced into local loopback (LLB) mode. In this loopback, data continues

to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data being transmitted.

Data in this loopback passes through the jitter attenuator (Figure 3-1

CCR4

Common Control Register 4

15 Hex

Bit # 7 6 5 4 3 2 1 0

Name LIRST RESA RESR RCM4 RCM3 RCM2 RCM1 RCM0

NAME BIT FUNCTION

LIRST 7

Line Interface Reset. Setting this bit from 0 to 1 initiates an internal reset

that affects the clock recovery state machine and jitter attenuator.

Normally this bit is only toggled on power-up. It must be cleared and set

again for a subsequent reset.

RESA 6

Receive Elastic Store Align. Setting this bit from 0 to 1 may force the

receive elastic store’s write/read pointers to a minimum separation of half

a frame. No action is taken if the pointer separation is already greater

than or equal to half a frame. If pointer separation is less than half a

frame, the command is executed and data is disrupted. This bit should be

toggled after SYSCLK has been applied and is stable. It must be cleared

and set again for a subsequent align. See Section 18

for details.

RESR 5

Receive Elastic Store Reset. Setting this bit from 0 to 1 forces the

receive elastic store to a depth of one frame. Receive data is lost during

the reset. The bit should be toggled after SYSCLK has been applied and

is stable. It must be cleared and set again for a subsequent reset. See

Section 18

for details.

RCM4 4

Receive Channel Monitor Bit 4. MSB of a channel decode that

determines which receive channel data appears in the RDS0M register.

See Section 10

for details.

RCM3 3

Receive Channel Monitor Bit 3

RCM2 2

Receive Channel Monitor Bit 2

RCM1 1

Receive Channel Monitor Bit 1

RCM0 0

Receive Channel Monitor Bit 0. LSB of the channel decode.