Datasheet

DS21Q59 Quad E1 Transceiver
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ADDRESS R/W NAME FUNCTION
37 R/W SA8 Signaling Access Register 8
38 R/W SA9 Signaling Access Register 9
39 R/W SA10 Signaling Access Register 10
3A R/W SA11 Signaling Access Register 11
3B R/W SA12 Signaling Access Register 12
3C R/W SA13 Signaling Access Register 13
3D R/W SA14 Signaling Access Register 14
3E R/W SA15 Signaling Access Register 15
3F R/W SA16 Signaling Access Register 16
Note 1: The device ID register and the system clock-interface control register exist in Transceiver 1 only (TS0, TS1 = 0).
Note 2: Only the factory uses the test register; this register must be cleared (set to all zeros) on power-up initialization to ensure proper
operation.
8. CONTROL, ID, AND TEST REGISTERS
The DS21Q59 operation is configured through a set of nine control registers. Typically, registers are only accessed
when the system is first powered up. Once the device has been initialized, the control registers only need to be
accessed when there is a change in the system configuration. There is one receive control register (RCR), one
transmit control register (TCR), and seven common control registers (CCR1 to CCR7). Each of these registers is
described in this section.
Address 0Fh has a device identification register (IDR). The four MSBs of this read-only register are fixed to 1 0 0 1,
indicating that a DS21Q59 E1 quad transceiver is present. The lower 4 bits of the IDR are used to identify the
revision of the device. This register exists in Transceiver 1 only (TS0, TS1 = 0).
The factory in testing the DS21Q59 uses the test register at addresses 1E. On power-up, the test register should
be set to 00h for the DS21Q59 to properly operate.
Register Name:
IDR
Register Description:
Device Identification Register
Register Address:
0F Hex
Bit # 7 6 5 4 3 2 1 0
Name 1 0 0 1 ID3 ID2 ID1 ID0
NAME BIT FUNCTION
1 7
Bit 7
0 6
Bit 6
0 5
Bit 5
1 4
Bit 4
ID3 3
Chip Revision Bit 3. MSB of a decimal code that represents the chip revision.
ID2 1
Chip Revision Bit 2
ID1 2
Chip Revision Bit 1
ID0 0
Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.