Datasheet

DS21Q58 E1 Quad Transceiver

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10.3 E-Bit/PRBS Bit-Error Counter

E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit

counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running

with CRC4 multiframe. These error count registers increment once each time the received E-bit is set to 0. Since

the maximum E-bit count in a one-second period is 1000, this counter cannot saturate. The counter is disabled

during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the

CAS level.

Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function is enabled.

In this mode, the counter is active when the receive PRBS detector can synchronize to the PRBS pattern. This

pattern can be framed, unframed, or in any time slot. See Section 13

for more details.

EBCR1, EBCR2

E-Bit Count Registers

04 Hex, 05 Hex

Bit # 7 6 5 4 3 2 1 0

EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8

Name

EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

NAME BIT FUNCTION

EB15 EBCR1.7 MSB of the 16-bit E-bit error count.

EB0 EBCR2.0 LSB of the 16-bit E-bit error count.

10.4 FAS Error Counter

FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit

counter that records word errors in the FAS in time slot 0. This counter is disabled when RLOS is high. FAS errors

are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4

multiframe level. Since the maximum FAS word error count in a one-second period is 4000, this counter cannot

saturate.

FASCR1, FASCR2

FAS Error Count Registers

06 Hex, 07 Hex

Bit # 7 6 5 4 3 2 1 0

FAS15 FAS14 FAS13 FAS12 FAS11 FAS10 FAS9 FAS8

Name

FAS7 FAS6 FAS5 FAS4 FAS3 FAS2 FAS1 FAS0

NAME BIT FUNCTION

FAS15 FASCR1.7 MSB of the 16-bit FAS error count.

FAS0 FASCR2.0 LSB of the 16-bit FAS error count.