Datasheet
DS21Q58 E1 Quad Transceiver
28 of 74
9.1 Interrupt Handling
The host can quickly determine which status registers in the four ports are causing an interrupt by reading one of
the unused addresses such as 0Ch, 0Dh, or 0Eh in any port.
Bit # 7 6 5 4 3 2 1 0
Name SR2P4 SR1P4 SR2P3 SR1P3 SR2P2 SR1P2 SR2P1 SR1P1
NAME BIT FUNCTION
SR2P4 7
Status Register 2, Port 4. A 1 in this bit position indicates that status register 2
in port 4 is asserting an interrupt.
SR1P4 6
Status Register 1, Port 4. A 1 in this bit position indicates that status register 1
in port 4 is asserting an interrupt.
SR2P3 5
Status Register 2, Port 3. A 1 in this bit position indicates that status register 2
in port 3 is asserting an interrupt.
SR1P3 4
Status Register 1, Port 3. A 1 in this bit position indicates that status register 1
in port 3 is asserting an interrupt.
SR2P2 3
Status Register 2, Port 2. A 1 in this bit position indicates that status register 2
in port 2 is asserting an interrupt.
SR1P2 2
Status Register 1, Port 2. A 1 in this bit position indicates that status register 1
in port 2 is asserting an interrupt.
SR2P1 1
Status Register 2, Port 1. A 1 in this bit position indicates that status register 2
in port 1 is asserting an interrupt.
SR1P1 0
Status Register 1, Port 1. A 1 in this bit position indicates that status register 1
in port 1 is asserting an interrupt.
Register Name:
RIR
Register Description:
Receive Information Register
Register Address:
08 Hex
Bit # 7 6 5 4 3 2 1 0
Name — — JALT RESF RESE CRCRC FASRC CASRC
NAME BIT FUNCTION
— 7
Unused
— 6
Unused
JALT 5
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to
within 4 bits of its limit; useful for debugging jitter attenuation operation.
RESF 4
Receive Elastic Store Full. Set when the receive elastic store buffer fills and a
frame is deleted.
RESE 3
Receive Elastic Store Empty. Set when the receive elastic store buffer
empties and a frame is repeated.
CRCRC 2
CRC Resync Criteria Met. Set when 915/1000 codewords are received in
error.
FASRC 1
FAS Resync Criteria Met. Set when three consecutive FAS words are
received in error.
CASRC 0
CAS Resync Criteria Met. Set when two consecutive CAS MF alignment
words are received in error.