Datasheet

DS21Q50
8 of 87
Figure 1-1. Block Diagram
RRING1
Receive-Side
Framer
Transmit-Side
Formatter
TCLK1
TSER1
RSER1
SYSCLK1
RSYNC1
Elastic Store
A
nd
IBO Buffer
TRING1
TTIP1
Jitter Attenuator
Either transmit or receive path
Receive
Line I/F
Clock / Data
Recovery
RTIP1
VCO/PLL
Transmit Line I/F
DATA
CLOCK
SYNC
SYNC
CLOCK
DATA
IBO
Buffer
Divide by
2/4/8
MCL
TSYNC1
Sync
Control
BU Ck
MUX
Tx Ck
MUX
A
B
A
B
C
User Outputs
Select
OUTA
OUTB
RCLK Transceiver 2
RCLK Transceiver 3
RCLK Transceiver 4
MUX
4/8/16MHz
Synthesizer
Backup Clock MUX
Transceivers 2, 3, and 4
4/8/16MCK
REFCLK
SYSTEM
INTERFACE
TRANSMIT
CLOCK SOURCE
TRANSCEIVER 1of 4
TRANSMIT
SIDE
RECEIVE
SIDE
Local Loopback
Remote Loopback
Framer Loopback
LOTC
Detect
2.048MHz
D0 to D7/
A
D0 to AD7
TS1
I
NT
W
R
(
R/
W
)
R
D
(
D
S
)
C
S
A
LE
(
AS
)
/A5
A
0 to A4
Parallel & Test Control Port
(routed to all blocks)
BTS
BTS
TS0
PBT
A
JACOI
A
JACKI
A
lternate
Jitter
A
ttenuato
r