Datasheet

DS21Q50
71 of 87
Figure 19-7. Transmit Interleave Bus Operation
TSER
LSB
SYSCLK
TSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
MSB LSB
FRAMER 1, CHANNEL 1
3
TSER
TSYNC
TSER
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
1
2
BIT DETAIL
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
NOTE 1: 4.096MHZ BUS CONFIGURATION.
NOTE 2: 8.192MHZ BUS CONFIGURATION.
NOTE 3: TSYNC IS IN THE INPUT MODE (TCR.0 = 0).