Datasheet

DS21Q50
69 of 87
Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled)
Figure 19-4. Receive Interleave Bus Operation
RSER
CHANNEL 1
SYSCLK
RSYNC
CHANNEL 31 CHANNEL 32
1
RSYNC
2
LSB MSB
LSB
MSB
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RCR.5 = 1).
RSER
LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
MSB LSB
FRAMER 1, CHANNEL 1
3
RSER
RSYNC
RSER
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
1
2
BIT DETAIL
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
NOTE 1: 4.096MHZ BUS CONFIGURATION.
NOTE 2: 8.192MHZ BUS CONFIGURATION.
NOTE 3: RSYNC IS IN THE INPUT MODE (RCR.5 = 0).