Datasheet

DS21Q50

46 of 87

9. SYSTEM CLOCK INTERFACE

A single system clock interface (SCI) is common to the four DS21Q50 transceivers. The SCI allows any

one of the four receivers to act as the master reference clock for the system. When multiple DS21Q50s

are used to build an N port system, the SCI allows any one of the N ports to be the master. The selected

reference is then distributed to the other DS21Q50s through the REFCLK pin. The REFCLK pin acts as

an output on the DS21Q50, which has been selected to provide the reference clock from one of its four

receivers. On DS21Q50s not selected to source the reference clock, this pin becomes an input by writing

0s to the SCSx bits. The reference clock is also passed to the clock synthesizer PLL to generate a

2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. This clock can then be used with the IBO

function to merge up to eight E1 lines onto a single high-speed PCM bus. If the master E1 port fails

(enters a receive carrier-loss condition), that port automatically switches to the clock present on the

MCLK pin. Therefore, MCLK acts as the backup source of master clock. The host can then find and

select a functioning E1 port as the master. Because the selected port’s clock is passed to the other

DS21Q50s in a multiple device configuration, one DS21Q50’s synthesizer can always be the source of

the high-speed clock. This allows smooth transitions when clock-source switching occurs. The SCI

control register exists in transceiver 1 only (TS0, TS1 = 0).

SCICR

only for transceiver 1 (TS0 = 0, TS1 = 0).

1D Hex

Bit 7 6 5 4 3 2 1 0

Name AJACKE BUCS SOE CSS1 CSS0 SCS2 SCS1 SCS0

NAME BIT FUNCTION

AJACKE 7 AJACK Enable. This bit enables the alternate jitter attenuator.

BUCS 6

Backup Clock Select. Selects which clock source to switch to automatically during a loss-

of-transmit clock event.

0 = During an LOTC event, switch to MCLK

1 = During an LOTC event, switch to system reference clock

SOE 5

Synthesizer Output Enable

0 = 2/4/8/16MCK pin in high-Z mode

1 = 2/4/8/16MCK pin active

CSS1 4 Clock Synthesizer Select Bit 1 (Table 9-2)

CSS0 3 Clock Synthesizer Select Bit 0 (Table 9-2)

SCS2 2 System Clock Select Bit 2 (Table 9-1)

SCS1 1 System Clock Select Bit 1 (Table 9-1)

SCS0 0 System Clock Select Bit 0 (Table 9-1)