Datasheet

DS21Q50
43 of 87
Register Name:
TDS0M
Register Description:
Transmit Ds0 Monitor Register
Register Address:
22 Hex
Bit 7 6 5 4 3 2 1 0
Name B1 B2 B3 B4 B5 B6 B7 B8
NAME BIT FUNCTION
B1 7
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be
transmitted).
B2 6 Transmit DS0 Channel Bit 2
B3 5 Transmit DS0 Channel Bit 3
B4 4 Transmit DS0 Channel Bit 4
B5 3 Transmit DS0 Channel Bit 5
B6 2 Transmit DS0 Channel Bit 6
B7 1 Transmit DS0 Channel Bit 7
B8 0
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be
transmitted).
Register Name: CCR4 (Repeated here from Section 3 for convenience.)
Register Description:
Common Control Register 4
Register Address:
15 Hex
Bit 7 6 5 4 3 2 1 0
Name LIRST RESA RESR RCM4 RCM3 RCM2 RCM1 RCM0
NAME BIT FUNCTION
LIRST 7 Line Interface Reset
RESA 6 Receive Elastic Store Align
RESR 5 Receive Elastic Store Reset
RCM4 4
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data appears in the RDS0M register.
See Section 6
or details.
RCM3 3 Receive Channel Monitor Bit 3
RCM2 2 Receive Channel Monitor Bit 2
RCM1 1 Receive Channel Monitor Bit 1
RCM0 0 Receive Channel Monitor Bit 0. LSB of the channel decode.