Datasheet

DS21Q50

40 of 87

6.2 CRC4 Error Counter

CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word

of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the

maximum CRC4 count in a one-second period is 1000, this counter cannot saturate. The counter is

disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe

sync occurs at the CAS level. CRCCR1 and CRCCR2 have alternate functions.

CRCCR1, CRCCR2

CRC4 Count Registers

02 Hex, 03 Hex

Bit 7 6 5 4 3 2 1 0

Name CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8

Name CRC7 CRC6 CRC5 CRC4 CRC/3 CRC2 CRC1 CRC0

NAME BIT FUNCTION

CRC15 CRCCR1.7 MSB of the 16-bit CRC4 error count

CRC0 CRCCR2.0 LSB of the 16-bit CRC4 error count

6.3 E-Bit/PRBS Bit Error Counter

E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a

16-bit counter that records far-end block errors (FEBE), as reported in the first bit of frames 13 and 15 on

E1 lines running with CRC4 multiframe. These error count registers increment once each time the

received E-bit is set to 0. Since the maximum E-bit count in a one-second period is 1000, this counter

cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues

to count if loss-of-multiframe sync occurs at the CAS level.

Alternately, this counter counts bit errors in the received PRBS pattern when the receive PRBS function

is enabled. In this mode, the counter is active when the receive PRBS detector can synchronize to the

PRBS pattern. This pattern can be framed, unframed, or in any time slot. See Section 8

for more details.

EBCR1, EBCR2

E-Bit Count Registers

04 Hex, 05 Hex

Bit 7 6 5 4 3 2 1 0

Name EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8

Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

NAME BIT FUNCTION

EB15 EBCR1.7 MSB of the 16-bit E-bit error count

EB0 EBCR2.0 LSB of the 16-bit E-bit error count