Datasheet

DS21Q50
33 of 87
Register Name:
RIR
Register Description:
Receive Information Register
Register Address:
08 Hex
Bit 7 6 5 4 3 2 1 0
Name RGM1 RGM0 JALT RESF RESE CRCRC FASRC CASRC
NAME BIT FUNCTION
RGM1 7 Receive Gain Monitor Bit 1. See the Level Indication table below for level indication.
RGM0 6 Receive Gain Monitor Bit 0. See the Level Indication table below for level indication.
JALT 5
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4 bits of
its limit; useful for debugging jitter attenuation operation.
RESF 4
Receive Elastic Store Full. Set when the receive elastic store buffer fills and a frame is
deleted.
RESE 3
Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a frame
is repeated.
CRCRC 2 CRC Resync Criteria Met. Set when 915/1000 codewords are received in error.
FASRC 1 FAS Resync Criteria Met. Set when three consecutive FAS words are received in error.
CASRC 0
CAS Resync Criteria Met. Set when two consecutive CAS MF alignment words are
received in error.
LEVEL INDICATION
RGM1 RGM0 LEVEL (dB)
0 0 0 to 10
0 1 10 to 20
1 0 20 to 30
1 1 >30