Datasheet

DS21Q50
28 of 87
4.2 Framer Loopback
When CCR1.7 is set to 1, the DS21Q50 enters a framer loopback (FLB) mode (Figure 1-1). This
loopback is useful in testing and debugging applications. In FLB, the SCT loops data from the transmitter
back to the receiver. When FLB is enabled, the following occurs:
1) Data is transmitted as normal at TTIP and TRING.
2) The RCLK output is replaced with the TCLK input.
Register Name:
CCR2
Register Description:
Common Control Register 2
Register Address:
13 Hex
Bit 7 6 5 4 3 2 1 0
Name RCUS VCRFS AAIS ARA RSERC LOTCMC RCLA TCSS
SYMBOL BIT FUNCTION
ECUS 7
Error Counter Update Select. See Section 6
for details.
0 = update error counters once a second
1 = update error counters every 62.5ms (500 frames)
VCRFS 6
VCR Function Select. See Section 6
for details.
0 = count bipolar violations (BPVs)
1 = count code violations (CVs)
AAIS 5
Automatic AIS Generation
0 = disabled
1 = enabled
ARA 4
Automatic Remote Alarm Generation
0 = disabled
1 = enabled
RSERC 3
RSER Control
0 = allow RSER to output data as received under all conditions
1 = force RSER to one under loss-of-frame alignment conditions
LOTCMC 2
Loss-of-Transmit Clock Mux Control. Determines whether the transmit formatter should
switch to the ever present RCLK if the TCLK should fail to transition (Figure 1-1
).
0 = do not switch to RCLK if TCLK stops
1 = switch to RCLK if TCLK stops
RCLA 1
Receive Carrier Loss (RCL) Alternate Criteria
0 = RCL declared upon 255 consecutive 0s (125ms)
1 = RCL declared upon 2048 consecutive 0s (1ms)
TCSS 0
Transmit Clock Source Select. This function allows the user to internally select RCLK as
the clock source for the transmit formatter.
0 = source of transmit clock determined by CCR2.2 (LOTCMC)
1 = force transmitter to internally switch to RCLK as source of transmit clock. Signal at
TCLK pin is ignored