Datasheet

DS21Q50

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ADDRESS R/W NAME FUNCTION

2C R/W PCLB2 Per-Channel Loopback Control 2

2D R/W PCLB3 Per-Channel Loopback Control 3

2E R/W PCLB4 Per-Channel Loopback Control 4

2F R/W TEST1 (set to 00h) Test 1 (Note 2)

Note 1:

The device ID register and the system clock interface control register exist in Transceiver 1 only. (TS0, TS1 = 0).

Note 2:

Only the factory uses the test registers; these registers must be cleared (set to all zeros) on power-up initialization to

ensure proper operation.

4. CONTROL, ID, AND TEST REGISTERS

The operation of the DS21Q50 is configured through a set of seven control registers. Typically, the

control registers are only accessed when the system is first powered up. Once the device has been

initialized, the control registers only need to be accessed when there is a change in the system

configuration. There is one receive control register (RCR), one transmit control register (TCR), and five

common control registers (CCR1 to CCR5). Each of these registers is described in this section.

There is a device identification register (IDR) at address 0Fh. The MSB of this read-only register is fixed

to 1, indicating that an E1 quad transceiver is present. The next three MSBs are reserved for future use.

The lower 4 bits of the device ID register are used to identify the revision of the device. This register

exists in Transceiver 1 only (TS0, TS1 = 0).

The test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On

power-up, the test registers should be set to 00h in order for the DS21Q50 to operate properly.

IDR

Device Identification Register

0F Hex

Bit 7 6 5 4 3 2 1 0

Name 1 0 0 0 ID3 ID2 ID1 ID0

BIT NAME FUNCTION

7 1 Bit 7

6 0 Bit 6

5 0 Bit 5

4 0 Bit 4

3 ID3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revision.

1 ID2 Chip Revision Bit 2

2 ID1 Chip Revision Bit 1

0 ID0 Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.