Datasheet

DS21Q50
20 of 87
3. HOST INTERFACE PORT
The DS21Q50 is controlled either through a nonmultiplexed bus, a multiplexed bus, or serial interface
bus by an external microcontroller or microprocessor. The device can operate with either Intel or
Motorola bus timing configurations. See Table 3-1 for a description of the bus configurations. All
Motorola bus signals are listed in parentheses (). See Functional Timing Diagrams in Section 19
for more
details.
Table 3-1. Bus Mode Select
PBTS BTS1 BTS0 PARALLEL PORT MODE
0 0 0 Intel Multiplexed
0 0 1 Intel Nonmultiplexed
1 0 0 Motorola Multiplexed
1 0 1 Motorola Nonmultiplexed
X 1 0 Serial
X 1 1 TEST (Outputs High-Z)
3.1 Parallel Port Operation
When using the parallel interface on the DS21Q50 (BTS1 = 0) the user has the option for either
multiplexed bus operation (BTS1 = 0, BTS0 = 0) or nonmultiplexed bus operation (BTS1 = 0, BTS0 = 1).
The DS21Q50 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is
wired low, Intel timing is selected; if wired high, Motorola timing is selected. All Motorola bus signals
are listed in parentheses (). See the timing diagrams in AC Timing Parameters and Diagrams in
Section 21 for more details.
3.2 Serial Port Operation
Setting BTS1 pin = 1 and the BTS0 pin = 0 enables the serial bus interface on the DS21Q50. Port
read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or
writes by the host. See Section 21 for the AC timing of the serial port. All serial port accesses are LSB
first. See Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4 for more details.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next five bits identify the register address. The next bit is reserved
and must be set to 0 for proper operation. The last bit (MSB) of the address/command byte enables the
burst mode when set to 1. The burst mode causes all registers to be consecutively written or read.
All data transfers are initiated by driving the CS input low. When input clock-edge select (ICES) is low,
input data is latched on the rising edge of SCLK. When ICES is high, input data is latched on the falling
edge of SCLK. When output clock-edge select (OCES) is low, data is output on the falling edge of
SCLK. When OCES is high, data is output on the rising edge of SCLK. Data is held until the next falling
or rising edge. All data transfers are terminated if the CS input transitions high. Port control logic is
disabled and SDO is three-stated when CS is high.