Datasheet

DS21Q50
18 of 87
Signal Name:
ICES
Signal Description:
Input Clock Edge Select
Signal Type:
Input
Used to select which SCLK clock edge samples data at SDI.
Signal Name:
OCES
Signal Description:
Output Clock Edge Select
Signal Type:
Input
Used to select which SCLK clock edge updates data at SDO.
Signal Name:
SCLK
Signal Description:
Serial Port Clock
Signal Type:
Input
Used to clock data into and out of the serial port.
2.1.6 Line Interface Pins
Signal Name:
MCLK
Signal Description:
Master Clock Input
Signal Type:
Input
A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation.
Signal Name:
RTIP and RRING
Signal Description:
Receive Tip and Ring
Signal Type:
Input
Analog inputs for clock recovery circuitry. These pins connect through a 1:1 transformer to the E1 line. See Section
16
for details.
Signal Name:
TTIP and TRING
Signal Description:
Transmit Tip and Ring
Signal Type:
Output
Analog line driver outputs. These pins connect through a 1:2 step-up transformer to the E1 line. See Section 16
for
details.
2.1.7 Supply Pins
Signal Name:
DVDD
Signal Description:
Digital Positive Supply
Signal Type:
Supply
3.3V ±5%. Should be tied to the RVDD and TVDD pins.
Signal Name:
RVDD
Signal Description:
Receive Analog Positive Supply
Signal Type:
Supply
3.3V ±5%. Should be tied to the DVDD and TVDD pins.
Signal Name:
TVDD
Signal Description:
Transmit Analog Positive Supply
Signal Type:
Supply
3.3V ±5%. Should be tied to the RVDD and DVDD pins.