Datasheet

DS2155
232 of 238
Figure 37-9. Receive-Side Timing, Elastic Store Enabled
Note 1: RSYNC is in the output mode.
Note 2: RSYNC is in the input mode.
Note 3: F-bit when MSTRREG.1 = 0, MSB of TS0 when MSTREG.1 = 1.
Figure 37-10. Receive Line Interface Timing
F
t
t
R
t
D3
t
D4
t
D4
t
D4
t
t
SU
HD
RSER / RSIG
RCHCLK
RCHBLK
1
RSYNC
2
RSYNC
RSYSCLK
SL
t
t
SP
SH
t
t
D4
RMSYNC
SEE NOTE 3
t
F
t
R
RPOSI, RNEGI
RCLKI
CL
t
t
CP
CH
t
t
SU
t
HD
t
DD
RPOSO, RNEGO
RCLKO
LL
t
t
LP
LH
t