Datasheet

DS2155
231 of 238
Figure 37-8. Receive-Side Timing
Note 1: RSYNC is in the output mode.
Note 2: Shown is RLINK/RLCLK in the ESF framing mode.
Note 3: No relationship between RCHCLK and RCHBLK and other signals is implied.
Note 4: RLCLK only pulses high during Sa bit locations as defined in the E1RCR2 register.
t
D1
1
t
D2
RSER / RDATA / RSIG
RCHCLK
RCHBLK
RSYNC
RLCLK
RLINK (T1MODE)
t
D1
RCLK
RFSYNC / RMSYNC
2
t
D2
t
D2
t
D2
t
D2
RLINK (E1 MODE)
Sa4 to Sa8
Bit Position
4
1ST FRAME BIT