Datasheet

DS2155

218 of 238

Figure 35-19. Transmit-Side Boundary Timing (Elastic Store Disabled)

Note 1: TSYNC is in the output mode (IOCR1.1 = 1).

Note 2: TSYNC is in the input mode (IOCR1.1 = 0).

Note 3: TCHBLK is programmed to block channel 2.

Note 4: TLINK is programmed to source the Sa4 bit.

Note 5: The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS MF alignment nibble (0000).

Note 6: Shown is a TNAF frame boundary.

Figure 35-20. Transmit-Side Boundary Timing, TSYSCLK = 1.544MHz

(Elastic Store Enabled)

Note 1:

The F-bit position in the TSER data is ignored.

Note 2: TCHBLK is programmed to block channel 24.

LSB MSB LSB MSB

CHANNEL 1 CHANNEL 2

ABCD

TCLK

TSER

TSYNC

TSIG

TCHCLK

TCHBLK

TLCLK

TLINK

DON'T CARE

Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8

DON'T CARE

LSB F MSBLSB MSB

CHANNEL 1CHANNEL 24

TSYSCLK

TSER

TSSYNC

TCHCLK

TCHBLK

CHANNEL 23