Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - telecommunication E1, HDLC, J1, T1 LQFP 100

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Figure 35-9. Transmit-Side 1.544MHz Boundary Timing (Elastic Store

Enabled)

Note 1:

TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG is ignored during channel 24).

Figure 35-10. Transmit-Side 2.048MHz Boundary Timing (Elastic Store

Enabled)

Note 1: TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored.

Note 2: TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored).

Note 3: TCHBLK is forced to 1 in the same channels as TSER is ignored (see Note 1).

Note 4: The F-bit position for the T1 frame is sampled and passed through the transmit-side elastic store into the MSB bit position of channel 1.

(Normally, the transmit-side formatter overwrites the F-bit position unless the formatter is programmed to pass through the F-bit

position.)

LSB F MSBLSB MSB

CHANNEL 1CHANNEL 24

ABC/AD/B ABC/AD/B

TSYSCLK

TSER

TSSYNC

TSIG

TCHCLK

TCHBLK

CHANNEL 23

CHANNEL 23 CHANNEL 24 CHANNEL 1

LSB

LSB MSB

CHANNEL 1CHANNEL 32