Datasheet

DS2155
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Table 34-B. ID Code Structure
MSB
LSB
Version
Contact Factory
Device ID JEDEC 1
4 bits 16 bits 00010100001 1
Table 34-C. Device ID Codes
PART 16-BIT ID
DS2155 0010h
DS2156 0019h
DS21354 0005h
DS21554 0003h
DS21352 0004h
DS21552 0002h
34.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the boundary scan register and the bypass register.
An optional test register, the identification register, has been included with the DS2155 design. It is used
with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
34.4 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital
I/O cells. It is n bits in length. See Table 34-D for cell bit locations and definitions.
34.5 Bypass Register
This is a single one-bit shift register used with the BYPASS, CLAMP, and HIGH-Z instructions that
provides a short path between JTDI and JTDO.
34.6 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
See Table 34-B
and Table 34-C for more information on bit usage.