Datasheet

DS2155
30 of 238
4.9 L and G Package Pinout
The DS2155 is available in either a 100-pin LQFP (L) or 10mm CSBGA, 0.8mm pitch (G) package.
Table 4-A. Pin Description Sorted by Pin Number
PIN
LQFP CSBGA
SYMBOL TYPE FUNCTION
1 A1 RCHBLK O Receive Channel Block
2 B2 JTMS I IEEE 1149.1 Test Mode Select
3 C3 BPCLK O Backplane Clock
4 B1 JTCLK I IEEE 1149.1 Test Clock Signal
5 D4 JTRST I IEEE 1149.1 Test Reset
6 C2 RCL O Receive Carrier Loss
7 C1 JTDI I IEEE 1149.1 Test Data Input
8 D3 UOP0 O User Output 0
9 D2 UOP1 O User Output 1
10 D1 JTDO O IEEE 1149.1 Test Data Output
11 E3 BTS I Bus Type Select
12 E2 LIUC I Line Interface Connect
13 E1 8XCLK O Eight Times Clock
14 E4 TSTRST I Test/Reset
15 E5 UOP2 O User Output 2
16 F1 RTIP I Receive Analog Tip Input
17 F2 RRING I Receive Analog Ring Input
18 F3 RVDD — Receive Analog Positive Supply
19, 20, 24 F4, G1, J1 RVSS — Receive Analog Signal Ground
21 G2 MCLK I Master Clock Input
22 H1 XTALD O Quartz Crystal Driver
23 G3 UOP3 O User Output 3
25 H2
INT
O Interrupt
26 K1 N.C. — Reserved for Factory Test
27, 28 J2, H3 N.C. — Reserved for Factory Test
29 K2 TTIP O Transmit Analog Tip Output
30 G4 TVSS – Transmit Analog Signal Ground
31 J3 TVDD – Transmit Analog Positive Supply
32 K3 TRING O Transmit Analog Ring Output
33 H4 TCHBLK O Transmit Channel Block
34 J4 TLCLK O Transmit Link Clock
35 K4 TLINK I Transmit Link Data
36 H5 ESIBS0 I/O Extended System Information Bus 0
37 J5 TSYNC I/O Transmit Sync
38 K5 TPOSI I Transmit Positive-Data Input
39 G5 TNEGI I Transmit Negative-Data Input
40 F5 TCLKI I Transmit Clock Input
41 K6 TCLKO O Transmit Clock Output
42 J6 TNEGO O Transmit Negative-Data Output
43 H6 TPOSO O Transmit Positive-Data Output
44, 61, 81, 83 K7, F8, B8, C7 DVDD — Digital Positive Supply
45, 60, 80, 84 G6, G10, D7, B7 DVSS — Digital Signal Ground
46 J7 TCLK I Transmit Clock
47 K8 TSER I Transmit Serial Data
48 H7 TSIG I Transmit Signaling Input
49 K9 TESO O Transmit Elastic Store Output
50 J8 TDATA I Transmit Data