Datasheet

DS2155
217 of 238
Figure 35-17. G.802 Timing, E1 Mode Only
Note 1: RCHBLK or TCHBLK programmed to pulse high during time slots 1 through 15, 17 through 25, and bit 1 of time slot 26.
Figure 35-18. Transmit-Side Timing
Note 1: TSYNC in frame mode (IOCR1.2 = 0).
Note 2: TSYNC in multiframe mode (IOCR1.2 = 1).
Note 3: TLINK is programmed to source just the Sa4 bit.
Note 4: This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame.
Note 5: TLINK and TLCLK are not synchronous with TSSYNC.
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TS #
RSYNC
TSYNC
RCHCLK
TCHCLK
RCHBLK
TCHBLK
CHANNEL 26
CHANNEL 25
LSB
MSB
RCLK / RSYSCLK
TCLK / TSYSCLK
RSER / TSER
RCHCLK / TCHCLK
RCHBLK / TCHBLK
120
12345 67891011 12
1
3
TSSYNC
FRAME#
TSYNC
TSYNC
13
14 15 16
12345
TLCLK
TLINK
14 15 16
678910
3
2