Datasheet

DS2155
213 of 238
35.2 E1 Mode
Figure 35-11. Receive-Side Timing
Note 1: RSYNC in frame mode (IOCR1.5 = 0).
Note 2: RSYNC in multiframe mode (IOCR1.5 = 1).
Note 3: RLCLK is programmed to output just the Sa bits.
Note 4: RLINK always outputs all five Sa bits as well as the rest of the receive data stream.
Note 5: This diagram assumes the CAS MF begins in the RAF frame.
Figure 35-12. Receive-Side Boundary Timing (with Elastic Store Disabled)
Note 1: RCHBLK is programmed to block channel 1.
Note 2: RLCLK is programmed to mark the Sa4 bit in RLINK.
Note 3: Shown is a RNAF frame boundary.
Note 4: RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1.
CHANNEL 32
CHANNEL 1 CHANNEL 2
CHANNEL 32
CHANNEL 1 CHANNEL 2
RCLK
RSER
RSYNC
RFSYNC
RSIG
RCHCLK
RCHBLK
1
RLCLK
RLINK
2
CD A
LSB
MSB
AB
Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
Sa4 Sa5 Sa6 Sa7 Sa8
B
Note 4
FRAME#
1
23456789101112131415161
4
RLINK
RLCLK
3
RSYNC
1
RSYNC
RFSYNC
2