Datasheet

DS2155

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30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER

The DS2155 contains an on-chip clock synthesizer that generates a user-selectable clock output on the

BPCLK pin, referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop

to generate low-jitter clocks. Common applications include generation of port and backplane system

clocks. The CCR2 register is used to enable (CCR2.0) and select (CCR2.1 and CCR2.2) the clock

frequency of the BPCLK pin.

CCR2

Common Control Register 2

71h

Bit # 7 6 5 4 3 2 1 0

Name BPCS1 BPCS0 BPEN

Default 0 0 0 0 0 0 0 0

Bit 0/Backplane Clock Enable (BPEN)

0 = disable BPCLK pin (pin held at logic 0)

1 = enable BPCLK pin

Bits 1, 2/Backplane Clock Selects (BPCS0, BPCS1)

BPCS1 BPCS0 BPCLK Frequency (MHz)

0 0 16.384

0 1 8.192

1 0 4.096

1 1 2.048

Bits 3 to 7/ Unused, must be set to 0 for proper operation

31. FRACTIONAL T1/E1 SUPPORT

The DS2155 can be programmed to output gapped clocks for selected channels in the receive and

transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-

PRI applications. The receive and transmit paths have independent enables. Channel formats supported

include 56kbps and 64kbps. This is accomplished by assigning an alternate function to the RCHCLK and

TCHCLK pins. Setting CCR3.0 = 1 causes the RCHCLK pin to output a gapped clock as defined by the

receive fractional T1/E1 function of the PCPR register. Setting CCR3.2 = 1 causes the TCHCLK pin to

output a gapped clock as defined by the transmit fractional T1/E1 function of the PCPR register. CCR3.1

and CCR3.3 can be used to select between 64kbps and 56kbps operation. See Section 7

for details about

programming the per-channel function. In T1 mode no clock is generated at the F-bit position.

When 56kbps mode is selected, the LSB clock in the channel is omitted. Only the seven most significant

bits of the channel have clocks.