Datasheet
DS2155
127 of 238
Table 23-A. HDLC Controller Registers
REGISTER FUNCTION
CONTROL AND CONFIGURATION
H1TC, HDLC #1 Transmit Control Register
H2TC, HDLC #2 Transmit Control Register
General control over the transmit HDLC
controllers
H1RC, HDLC #1 Receive Control Register
H2RC, HDLC #2 Receive Control Register
General control over the receive HDLC
controllers
H1FC, HDLC #1 FIFO Control Register
H2FC, HDLC #2 FIFO Control Register
Sets high watermark for receiver and low
watermark for transmitter
STATUS AND INFORMATION
SR6, HDLC #1 Status Register
SR7, HDLC #2 Status Register
Key status information for both transmit and
receive directions
IMR6, HDLC #1 Interrupt Mask Register
IMR7, HDLC #2 Interrupt Mask Register
Selects which bits in the status registers (SR7
and SR8) cause interrupts
INFO4, HDLC #1 and #2 Information Register
INFO5, HDLC #1 Information Register
INFO6, HDLC #2 Information Register
Information about HDLC controller
H1RPBA, HDLC #1 Receive Packet Bytes
Available Register
H2RPBA, HDLC #2 Receive Packet Bytes
Available Register
Indicates the number of bytes that can be read
from the receive FIFO
H1TFBA, HDLC #1 Transmit FIFO Buffer
Available Register
H2TFBA, HDLC #2 Transmit FIFO Buffer
Available Register
Indicates the number of bytes that can be
written to the transmit FIFO
MAPPING
H1RCS1, H1RCS2, H1RCS3, H1RCS4, HDLC
#1 Receive Channel Select Registers
H2RCS1, H2RCS2, H2RCS3, H2RCS4, HDLC
#2 Receive Channel Select Registers
Selects which channels are mapped to the
receive HDLC controller
H1RTSBS, HDLC #1 Receive TS/Sa Bit Select
Register
H2RTSBS, HDLC #2 Receive TS/Sa Bit Select
Register
Selects which bits in a channel are used or
which Sa bits are used by the receive HDLC
controller
H1TCS1, H1TCS2, H1TCS3, H1TCS4, HDLC
#1 Transmit Channel Select Registers
H2TCS1, H2TCS2, H2TCS3, H2TCS4, HDLC
#2 Transmit Channel Select Registers
Selects which channels are mapped to the
transmit HDLC controller
H1TTSBS, HDLC # 1 Transmit TS/Sa Bit Select
Register
H2TTSBS, HDLC # 2 Transmit TS/Sa Bit Select
Register
Selects which bits in a channel are used or
which Sa bits are used by the transmit HDLC
controller
FIFOs
H1RF, HDLC #1 Receive FIFO Register
H2RF, HDLC #1 Receive FIFO Register
Access to 128-byte receive FIFO
H1TF, HDLC #1 Transmit FIFO Register
H2TF, HDLC #2 Transmit FIFO Register
Access to 128-byte transmit FIFO