Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
9 of 124
2. BLOCK DIAGRAM
Figure 2-1. DS21354/554 Block Diagram
Receive Side
Framer
Transmit Side
Formatter
Elastic
Store
TSYNC TCLK TCHCLK
TSER
TCHBLK
RCHCLK RCHBLK RMSYNC
TSSYNC TSYSCLK
RSER RSYSCLK RSYNC RFSYNC
TLINK TLCLK
Timing Control
Elastic
Store
Sync Control
Timing Control
RLOS/LOTC
Signaling
Buffer
Hardware Signaling Insertion
TSIG
RSIGF
RCL
Local Loopback
TRING
TTIP
Jitter Attenuator
Either transmit or receive path
Receive
Line I/F
Clock / Data
Recovery
RRING
RTIP
Remote Loopback
VCO / PLL
MCLK
8XCLK
8MCLK
8.192MHz Clock
Synthesizer
32.768MHz
16.384 MHz
XTALD
RCLK
RPOSO
RNEGO
RNEGI
RPOSI
TPOSI
TNEGI
TNEGO
TPOSO
TESO TDATA
RCLKO
RCLKI
RDATA
TCLKI
TCLKO
LIUC
LIUC
Parallel & Test Control Port
(routed to all blocks)
D0 to D7 /
AD0 to AD7
BTS
INT*
WR*(R/W*)
RD*(DS*)
CS*
TEST
ALE(AS) / A7
A0 to A6
MUX
8
7
Interleave Bus
CI
RSYSCLK
Interleave Bus
MUX
MUX
T
r
a
n
s
m
i
t
L
i
n
e
I
/
F
DATA
CLOCK
SYNC
Framer Loopback
HDLC/BOC Controller Sa / DS0
LOTC MUX
HDLC/BOC Controller Sa / DS0
SYNC
CLOCK
DATA
CO
JTAG PORT
J
R
S
T
*
JTMS
JTCLK
JTDI
JTDO
RLINK RLCLK RSIG
Sa
DS21354
/
DS21554