Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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15. LINE INTERFACE FUNCTIONS
The line interface function in the DS21354/DS21554 contains three sections: (1) the receiver, which
handles clock and data recovery; (2) the transmitter, which waveshapes and drives the E1 line; and (3) the
jitter attenuator. Each of these three sections is controlled by The Line Interface Control Register (LICR)
contrlls each of these three sections.
LICR: LINE INTERFACE CONTROL REGISTER (Address = 18 Hex)
(MSB) (LSB)
L2 L1 L0 EGL JAS JABDS DJA TPD
SYMBOL POSITION NAME AND DESCRIPTION
L2 LICR.7
Line Build-Out Select Bit 2. Sets the transmitter build out (see Table 15-1
and Table 15-2).
L1 LICR.6
Line Build-Out Select Bit 1. Sets the transmitter build out (see Table 15-1
and Table 15-2
).
L0 LICR.5
Line Build-Out Select Bit 0. Sets the transmitter build out (see Table 15-1
and Table 15-2).
EGL LICR.4
Receive Equalizer Gain Limit.
0 = -12dB
1 = -43dB
JAS LICR.3
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS LICR.2
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA LICR.1
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD LICR.0
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and TRING pins