Datasheet
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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1. INTRODUCTION
The DS21354/DS21554 are superset versions of the popular DS2153 and DS2154 SCTs offering the new
features listed below. All the original features of the DS2153 and DS2154 have been retained, and the
software created for the original devices is transferable into the DS21354/DS21554.
New Features in the DS21354 and DS21554
FEATURE SECTION
HDLC controller with 64-Byte Buffers for Sa Bits or DS0s or Sub DS0s 14
Interleaving PCM Bus Operation 17
IEEE 1149.1 JTAG-Boundary Scan Architecture 16
3.3V (DS21354 Only) Supply 1.1 and 2
Line Interface Support for the G.703 2.048 Synchronization Interface 15
Customer Disconnect Indication (...101010...) Generator 5.6
Open-Drain Line Driver Option 5.6
Additional Features in the DS21354 and DS21554
FEATURE SECTION
Option for nonmultiplexed bus operation 1.1 and 20.2
Crystal-less jitter attenuation 15.3
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing Interrupt generated on change of signaling data
9
Improved receive sensitivity: 0 to -43dB 1.1
Per-channel code insertion in both transmit and receive paths 10
Expanded access to Sa and Si bits 13
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state 6
8.192MHz clock synthesizer 1.1
Per-channel loopback 10
Addition of hardware pins to indicate carrier loss and signaling freeze 1.1
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able to corrupt data and insert framing errors, CRC errors, etc.
1.1
Transmit and receive elastic stores now have independent backplane clocks 1.1
Ability to monitor one DS0 channel in both the transmit and receive paths 8
Access to the data streams in between the framer/formatter and the elastic stores 1.1
AIS generation in the line interface that is independent of loopbacks 1.1 and 5
Transmit current limiter to meet the 50mA short circuit requirement 15
Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 5.4
Automatic RAI generation to ETS 300 011 specifications 5.4