Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
117 of 124
20.3. Receive-Side AC Characteristics
AC CHARACTERISTICS—RECEIVE SIDE
(V
DD
= 3.3V ±5%, T
A
= 0°C to +70°C; for DS21354L; V
DD
= 5.0V ±5%, T
A
= 0°C to +70°C for DS21554L;
V
DD
= 3.3V ±5%, T
A
= -40°C to +85°C for DS21354LN; V
DD
= 5.0V ±5%, T
A
= -40°C to +85°C for DS21554LN.)
(See Figure 20-8
to Figure 20-10.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
RCLKO Period t
LP
488 ns
t
LH
200 244 ns 1
RCLKO Pulse Width
t
LL
200 244 ns 1
t
LH
150 244 ns 2
RCLKO Pulse Width
t
LL
150 244 ns 2
RCLKI Period t
CP
488 ns
t
CH
75 ns
RCLKI Pulse Width
t
CL
75 ns
t
SP
100 648 ns 3
t
SP
100 488 ns 4
t
SP
100 244 ns 5
RSYSCLK Period
t
SP
100 122 ns 6
t
SH
50 ns
RSYSCLK Pulse Width
t
SL
50 ns
RSYNC Setup to RSYSCLK Falling t
SU
20 t
SH
–5 ns
RSYNC Pulse Width t
PW
50 ns
RPOSI/RNEGI Setup to RCLKI Falling t
SU
20 ns
RPOSI/RNEGI Hold From RCLKI
Falling
t
HD
20 ns
RSYSCLK/RCLKI Rise and Fall Times t
R
, t
F
25 ns
Delay RCLKO to RPOSO, RNEGO
Valid
t
DD
50 ns
Delay RCLK to RSER, RDATA, RSIG,
RLINK Valid
t
D1
50 ns
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC, RLCLK
t
D2
50 ns
Delay RSYSCLK to RSER, RSIG Valid t
D3
50 ns
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC, CO
t
D4
50 ns
CI Setup to RSYSCLK Rising t
SC
20 ns
CI Pulse Width t
WC
50 ns
Note 1: Jitter attenuator enabled in the receive path.
Note 2: Jitter attenuator disabled or enabled in the transmit path.
Note 3: RSYSCLK = 1.544MHz.
Note 4: RSYSCLK = 2.048MHz.
Note 5: RSYSCLK = 4.096MHz.
Note 6: RSYSCLK = 8.192MHz.