Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
104 of 124
18.2. Transmit
Figure 18-7. Transmit-Side Timing
Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)
12345 67891011 12
1
3
TSSYNC
FRAME#
TSYNC
TSYNC
13
14 15 16
12345
TLCLK
TLINK
14 15 16
678910
3
2
NOTE 1: TSYNC IN FRAME MODE (TCR1.1 = 0).
NOTE 2: TSYNC IN MULTIFRAME MODE (TCR1.1 = 1).
NOTE 3: TLINK IS PROGRAMMED TO SOURCE JUST THE SA4 BIT.
NOTE 4: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC4 MF BEGIN WITH THE TAF FRAME.
NOTE 5: TLINK AND TLCLK ARE NOT SYNCHRONOUS WITH TSSYNC.
LSB MSB LSB MSB
CHANNEL 1 CHANNEL 2
CHANNEL 1 CHANNEL 2
ABCD
TCLK
TSER
TSYNC
TSYNC
TSIG
TCHCLK
TCHBLK
TLCLK
TLINK
1
2
3
4
DON'T CARE
Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8
D
DON'T CARE
4
NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR1.0 = 1).
NOTE 2: TSYNC IS IN THE INPUT MODE (TCR1.0 = 0).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 4: TLINK IS PROGRAMMED TO SOURCE THE SA4 BIT.
NOTE 5: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT
FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000).
NOTE 6: SHOWN IS A TNAF FRAME BOUNDARY.