Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
103 of 124
Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32
RSER
LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RS I G
FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
3
RSER
RSYNC
RS I G
RSER
RS I G
1
1
2
2
BIT DETAIL
ABC/AD/B ABC/AD/B ABC/AD/B
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
NOTE 1: 4.096MHz BUS CONFIGURATION.
NOTE 2: 8.192MHz BUS CONFIGURATION.
NOTE 3: RSYNC IS IN THE INPUT MODE (RCR1.5 = 0).