Datasheet

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
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4. PARALLEL PORT
The DS21354/DS21554 are controlled through either a nonmultiplexed (MUX = 0) or a multiplexed
(MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel
or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing is selected; if tied high,
Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams
in Section 18 for more details.
4.1. Register Map
Table 4-1. Register Map Sorted by Address
ADDRESS TYPE REGISTER NAME
00 R BPV or Code Violation Count 1 VCR1
01 R BPV or Code Violation Count 2 VCR2
02 R CRC4 Error Count 1/FAS Error Count 1 CRCCR1
03 R CRC4 Error Count 2 CRCCR2
04 R E-Bit Count 1/FAS Error Count 2 EBCR1
05 R E-Bit Count 2 EBCR2
06 R/W Status 1 SR1
07 R/W Status 2 SR2
08 R/W Receive Information RIR
09 — Not used (set to 00h)
0A — Not used (set to 00h)
0B — Not used (set to 00h)
0C — Not used (set to 00h)
0D — Not used (set to 00h)
0E — Not used (set to 00h)
0F R Device ID IDR
10 R/W Receive Control 1 RCR1
11 R/W Receive Control 2 RCR2
12 R/W Transmit Control 1 TCR1
13 R/W Transmit Control 2 TCR2
14 R/W Common Control 1 CCR1
15 R/W Test 1 TEST1 (set to 00h)
16 R/W Interrupt Mask 1 IMR1
17 R/W Interrupt Mask 2 IMR2
18 R/W Line Interface Control Register LICR
19 R/W Test 2 TEST2 (set to 00h)
1A R/W Common Control 2 CCR2
1B R/W Common Control 3 CCR3
1C R/W Transmit Sa Bit Control TSaCR
1D R/W Common Control 6 CCR6
1E R Synchronizer Status SSR
1F R Receive Non-Align Frame RNAF
20 R/W Transmit Align Frame TAF
21 R/W Transmit Non-Align Frame TNAF
22 R/W Transmit Channel Blocking 1 TCBR1
23 R/W Transmit Channel Blocking 2 TCBR2
24 R/W Transmit Channel Blocking 3 TCBR3