Datasheet

DS21352/DS21552
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The DS21352/552 are enhanced versions of the DS2152 and are backward pin-compatible. The JTAG
feature uses pins that had no function in the DS2152. When using the JTAG feature, be sure FMS (pin
76) is tied LOW enabling the newly defined pins of the DS21352/552. Details on Boundary Scan
Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE
1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM
+V
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
JTDI JTMS JTCLK
JTRST JTDO
+V +V
Test Access Port
Controller
MUX
10K 10K 10K
Select
Output Enable