Datasheet

DS21352/DS21552

97 of 137

18. TRANSMIT TRANSPARENCY

Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or

in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data in

the channels. Transparency can be invoked on a channel by channel basis by properly setting the TTR1,

TTR2, and TTR3 registers.

TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER (Address=39 to

3B Hex)

(MSB) (LSB)

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TTR1 (39)

CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TTR2 (3A)

CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TTR3 (3B)

SYMBOLS POSITIONS NAME AND DESCRIPTION

CH1-24 TTR1.0-3.7

Transmit Transparency Registers.

0 = this DS0 channel is not transparent

1 = this DS0 channel is transparent

Each of the bit position in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0

channel in the outgoing frame. When these bits are set to a one, the corresponding channel is transparent

(or clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the

channel have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a

zero when a Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from

determining which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set

to one, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR

registers are programmed. In this manner, the TTR registers are only affecting which channels are to have

robbed bit signaling inserted into them.

19. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT

19.1 DESCRIPTION

The DS21352/552 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,

BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See

Figure 19-1. The DS21352/552 contains the following as required by IEEE 1149.1 Standard Test Access