Datasheet

DS21352/DS21552
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The framer also contains a zero destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than 5 ones should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the
DS21352/552 will automatically look for 5 ones in a row, followed by a zero. If it finds such a pattern, it
will automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a
zero, the zero is not removed. The CCR2.0 bit should always be set to a one when the DS21352/552 is
extracting the FDL. More on how to use the DS21352/552 in FDL applications in this legacy support
mode is covered in a separate Application Note.
RFDL: RECEIVE FDL REGISTER (Address=28 Hex)
(MSB) (LSB)
RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
SYMBOL POSITION NAME AND DESCRIPTION
RFDL7 RFDL.7 MSB of the Received FDL Code
RFDL0 RFDL.0 LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is
received first.
RFDLM1: RECEIVE FDL MATCH REGISTER 1 (Address=29 Hex)
RFDLM2: RECEIVE FDL MATCH REGISTER 2 (Address=2A Hex)
(MSB) (LSB)
RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0
SYMBOL POSITION NAME AND DESCRIPTION
RFDL7 RFDL.7 MSB of the FDL Match Code
RFDL0 RFDL.0 LSB of the FDL Match Code
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers (RFDLM1/RFDLM2),
SR2.2 will be set to a one and the INT will go active if enabled via IMR2.2.