Datasheet

DS21352/DS21552
60 of 137
11.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 11.1 was a
feature contained in the original DS2151 while the second method which is covered in Section 11.2 is a
new feature of the DS2152/352/552.
11.1.1 FIXED PER-CHANNEL IDLE CODE INSERTION
The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 24 T1 channels. If this method is
used, then the CCR4.0 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the
outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed bit signaling and Bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)
[Also used for Per–Channel Loopback]
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TIR1 (3C)
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TIR2 (3D)
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TIR3 (3E)
SYMBOLS POSITIONS NAME AND DESCRIPTION
CH1-24 TIR1.0-3.7
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 3-1.
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
(MSB) (LSB)
TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0
SYMBOL POSITION NAME AND DESCRIPTION
TIDR7 TIDR.7 MSB of the Idle Code (this bit is transmitted first)
TIDR0 TIDR.0 LSB of the Idle Code (this bit is transmitted last)
11.1.2 UNIQUE PER-CHANNEL IDLE CODE INSERTION
The second method involves using the Transmit Channel Control Registers (TCC1/2/3) to determine which of the 24 T1
channels should be overwritten with the code placed in the Transmit Channel Registers (TC1 to TC24). This method is more
flexible than the first in that it allows a different 8–bit code to be placed into each of the 24 T1 channels.