Datasheet

DS21352/DS21552
36 of 137
3. All receive side signals will take on timing synchronous with TCLK instead of RCLKI.
Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this
will cause an unstable condition.
CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex)
(MSB) (LSB)
TFM TB8ZS TSLC96 TFDL RFM RB8ZS RSLC96 RZSE
SYMBOL POSITION NAME AND DESCRIPTION
TFM CCR2.7
Transmit Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
TB8ZS CCR2.6
Transmit B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
TSLC96 CCR2.5 Transmit SLC–96 / Fs–Bit Insertion Enable. Only set this bit to a one in D4 framing
applications. Must be set to one to source the Fs pattern from the TFDL register. See
Section 15.5 for details.
0 = SLC–96/Fs–bit insertion disabled
1 = SLC–96/Fs–bit insertion enabled
TFDL CCR2.4 Transmit FDL Zero Stuffer Enable. Set this bit to zero if using the internal
HDLC/BOC controller instead of the legacy support for the FDL. See Section 15 for
details.
0 = zero stuffer disabled
1 = zero stuffer enabled
RFM CCR2.3
Receive Frame Mode Select.
0 = D4 framing mode
1 = ESF framing mode
RB8ZS CCR2.2
Receive B8ZS Enable.
0 = B8ZS disabled
1 = B8ZS enabled
RSLC96 CCR2.1 Receive SLC–96 Enable. Only set this bit to a one in D4/SLC–96 framing
applications. See Section 15.5 for details.
0 = SLC–96 disabled
1 = SLC–96 enabled
RZSE CCR2.0 Receive FDL Zero Destuffer Enable. Set this bit to zero if using the internal
HDLC/BOC controller instead of the legacy support for the FDL. See Section 15.4 for
details.
0 = zero destuffer disabled
1 = zero destuffer enabled
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB) (LSB)
RESMDM TCLKSRC RLOSF RSMS PDE ECUS TLOOP TESMDM
SYMBOL POSITION NAME AND DESCRIPTION
RESMDM CCR3.7 Receive Elastic Store Minimum Delay Mode. See Section 14.4 for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
TCLKSRC CCR3.6 Transmit Clock Source Select. This function allows the user to internally select
RCLK as the clock source for the transmit side formatter.
0 = Source of transmit clock determined by TCR1.7 (LOTCMC)
1 = Force transmitter to internally switch to RCLK as source of transmit clock. Signal
at TCLK pin is ignored
RLOSF CCR3.5
Function of the RLOS/LOTC Output.
0 = Receive Loss of Sync (RLOS)