Datasheet

DS21352/DS21552
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Table 6-1 DEVICE ID BIT MAP
SCT T1/E1 Bit 6 Bit 5 Bit 4
DS2152 0 0 0 0
DS21352 0 0 0 1
DS21552 0 0 1 0
DS2154 1 0 0 0
DS21354 1 0 0 1
DS21554 1 0 1 0
The lower four bits of the IDR are used to display the die revision of the chip.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB) (LSB)
LCVCRF ARC OOF1 OOF2 SYNCC SYNCT SYNCE RESYNC
SYMBOL POSITION NAME AND DESCRIPTION
LCVCRF RCR1.7
Line Code Violation Count Register Function Select.
0 = do not count excessive zeros
1 = count excessive zeros
ARC RCR1.6
Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
OOF1 RCR1.5
Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
OOF2 RCR1.4
Out Of Frame Select 2.
0 = follow RCR1.5
1 = 2/6 frame bits in error
SYNCC RCR1.3
Sync Criteria.
In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode.
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
SYNCT RCR1.2
Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
SYNCE RCR1.1
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
RESYNC RCR1.0 Resync. When toggled from low to high, a resynchronization of the receive side framer
is initiated. Must be cleared and set again for a subsequent resync.