Datasheet

DS21352/DS21552
136 of 137
Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED
Figure 24-13 TRANSMIT LINE INTERFACE TIMING
t
F
t
R
TSYSCLK
TSER
TCHCLK
t
t
SL
t
SH
SP
TSSYNC
TCHBLK
t
D3
t
D3
t
t
t
SU
HD
SU
t
HD
Notes:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
TCLKO
TPOSO, TNEGO
t
DD
t
F
t
R
TCLKI
TPOSI, TNEGI
t
t
LL
t
LH
LP
t
HD
t
SU