Datasheet

DS21352/DS21552
132 of 137
Figure 24.9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED
F
t
t
R
t
D3
t
D4
t
D4
t
D4
t
t
SU
HD
RSER / RSIG
RCHCLK
RCHBLK
1
RSYNC
2
RSYNC
Notes:
1. RSYNC is in the output mode (RCR2.3 = 0)
2. RSYNC is in the input mode (RCR2.3 = 1)
3. F-BIT when CCR1.3 = 0, MSB of TS0 when CCR1.3 = 1
RSYSCLK
SL
t
t
SP
SH
t
t
D4
RMSYNC / CO
t
SC
CI
t
WC
SEE NOTE 3