Datasheet

DS21352/DS21552
130 of 137
24.3 RECEIVE SIDE AC CHARACTERISTICS
AC CHARACTERISTICS –
RECEIVE SIDE
[See Figure 24-8 to Figure 24-10]
(0°C to 70°C; V
DD
= 3.3V ± 5% for DS21352L;
0°C to 70°C; V
DD
= 5.0V ± 5% for DS21552L;
-40°C to +85°C; V
DD
= 3.3V ± 5% for DS21352LN;
-40°C to +85°C; V
DD
= 5.0V ± 5% for DS21552LN)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
RCLKO Period t
LP
648 ns
RCLKO Pulse Width t
LH
t
LL
200
200
324
324
ns
ns
1
1
RCLKO Pulse Width t
LH
t
LL
150
150
324
324
ns
ns
2
2
RCLKI Period t
CP
648 ns
RCLKI Pulse Width t
CH
t
CL
75
75
ns
ns
RSYSCLK Period t
SP
t
SP
t
SP
t
SP
100
100
100
100
648
488
244
122
ns
ns
ns
ns
3
4
5
6
RSYSCLK Pulse Width t
SH
t
SL
50
50
ns
ns
RSYNC Set Up to RSYSCLK Falling t
SU
20 t
SH
–5 ns
RSYNC Pulse Width t
PW
50 ns
RPOSI/RNEGI Set Up to RCLKI
Falling
t
SU
20 ns
RPOSI/RNEGI Hold From RCLKI
Falling
t
HD
20 ns
RSYSCLK/RCLKI Rise and Fall
Times
t
R
, t
F
25 ns
Delay RCLKO to RPOSO, RNEGO
Valid
t
DD
50 ns
Delay RCLK to RSER, RDATA,
RSIG, RLINK Valid
t
D1
50 ns
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC, RLCLK
t
D2
50 ns
Delay RSYSCLK to RSER, RSIG
Valid
t
D3
50 ns
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC, CO
t
D4
50 ns
CI Set Up to RSYSCLK Rising t
SC
20 ns
CI Pulse Width t
WC
50 ns
NOTES:
1. Jitter attenuator enabled in the receive path. 4. RSYSCLK = 2.048 MHz.
2. Jitter attenuator disabled or enabled in the transmit path. 5. RSYSCLK = 4.096 MHz
3. RSYSCLK = 1.544 MHz. 6. RSYSCLK = 8.192 MHz
Figure24-8 RECEIVE SIDE TIMING