Datasheet

DS21352/DS21552
125 of 137
Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX = 1)
Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1)
ASH
PW
t
CYC
t
ASD
t
ASD
PW
PW
EH
EL
t
t
t
t
t
t
AHL
CH
CS
ASL
ASED
CS*
A
D0-AD7
DHR
t
DDR
ALE
RD*
WR*
ASH
PW
t
CYC
t
ASD
t
ASD
PW
PW
EH
EL
t
t
t
t
t
t
t
AHL
DSW
DHW
CH
CS
ASL
ASED
CS*
A
D0-AD7
RD*
WR*
ALE