Datasheet

DS21352/DS21552
120 of 137
Figure 21-14 TRANSMIT INTERLEAVE BUS OPERATION, FRAME MODE
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
TSER
TSYSCLK
TSSYNC
TSIG
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1 FRAMER 0, CHANNEL 2
FRAMER 3, CHANNEL 32
FRAMER 0, CHANNEL 1
FRAMER 0, CHANNEL 2
BIT DETAIL
LSB
MSB
LSB
MSB
LSB
BC/AD/B
A
BC/AD/B
A
A
BC/AD/B
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32
TSER
1
TSSYNC
TSIG
1
TSER
2
TSIG
2
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR3 CH1-32