Datasheet

DS21352/DS21552

118 of 137

Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic

store enabled)

Notes:

1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored

2. TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG

will be ignored).

3. TCHBLK is forced to one in the same channels as TSER is ignored (see Note 1)

4. The F-bit position for the T1 frame is sampled and passed through the transmit side elastic store into

the MSB bit position of channel 1. (normally the transmit side formatter overwrites the F-bit

position unless the formatter is programmed to pass-through the F-bit position)

LSB

LSB MSB

CHANNEL 1CHANNEL 32

ABC/AD/B ABC/AD/B

TSYSCLK

TSER

TSSYNC

TSIG

TCHCLK

TCHBLK

CHANNEL 31

CHANNEL 31 CHANNEL 32 CHANNEL 1

2,3