Datasheet

DS21352/DS21552
114 of 137
Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 0).
RSER
LSB
RSYSCLK
RSYNC
3
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSIG
FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 2
BIT DETAIL
A
BC/AD/B
A
BC/AD/B
A
BC/AD/B
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32
RSER
1
RSYNC
RSIG
RSER
RSIG
2
2
FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32 FR2 CH1-32
FR3 CH1-32
FR0 CH1-32 FR1 CH1-32 FR2 CH1-32
FR3 CH1-32