Datasheet

DS21352/DS21552

112 of 137

Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store

enabled)

Notes:

1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one

2. RSYNC is in the output mode (RCR2.3 = 0)

3. RSYNC is in the input mode (RCR2.3 = 1)

4. RCHBLK is forced to one in the same channels as RSER (see Note 1)

5. The F-Bit position is passed through the receive side elastic store

RSER

CHANNEL 1

RCHCLK

RCHBLK

RSYSCLK

RSYNC

CHANNEL 31 CHANNEL 32

RSYNC

RMSYNC

RSIG

CHANNEL 31

CHANNEL 32

C/A

D/B

C/A

D/B

CHANNEL 1

LSB MSB

LSB