Datasheet

DS21352/DS21552
111 of 137
Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)
Notes:
1. RCHBLK is programmed to block channel 24
2. Shown is RLINK/RLCLK in the ESF framing mode
Figure 21-4 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store
enabled)
Notes:
1. RSYNC is in the output mode (RCR2.3 = 0)
2. RSYNC is in the input mode (RCR2.3 = 1)
3. RCHBLK is programmed to block channel 24
CHANNEL 23
CHANNEL 24 CHANNEL 1
CHANNEL 23
CHANNEL 24 CHANNEL 1
RCLK
RSER
RSYNC
RFSYNC
RSIG
RCHCLK
RCHBLK
1
RLCLK
RLINK
2
BA
C/A
D/B
AC/A
D/B
LSB
F
MSB
MSB
LSB
AB
RSER
CHANNEL 23
CHANNEL 24 CHANNEL 1
RCHCLK
RCHBLK
RSYSCLK
RSYNC
2
3
RSYNC
1
RMSYNC
RSIG
LSB
F
MSB
MSB
LSB
CHANNEL 23 CHANNEL 24
CHANNEL 1
BA
C/A
D/B
AC/A
D/B
AB