Datasheet
DS2148/DS21Q48
9 of 73
Figure 1-3. Transmit Logic
BPV
Insert
mux
B8ZS/
HDB3
Coder
Logic
Error
Insert
mux
OR
Gate
OR
Gate
CCR3.1
CCR1.6
CCR2.2
CCR3.0
CCR3.4
CCR3.3
TPOS
TNEG
To
Remote
Loopback
PRBS Generator
Loop Code Generator
Clock
Invert
Loss Of Transmit
Clock Detect
TCLK
CCR2.1
RCLK
JACLK
(derived
from
MCLK)
CCR1.0
CCR1.1
CCR1.2
1
0
mux
mux
OR
Gate
To LOTC Output Pin
0
1
0
1
AND
Gate
Routed to
All Blocks
tx bd
SR.5










